The present invention relates to a detector for the sub signal of a modulated AM stereophonic signal. More particularly, the invention relates to a sub signal detector for use in a circuit for demodulating compatible quadrature AM stereophonic signals that can also be received by a monophonic AM receiver.
A modulated AM stereophonic signal e.sub.s (t) supplied by a compatible quadrature PM system can gradually be represented by the following formulas: EQU e.sub.s (t)={1+L(t)+R(t)} cos (.omega..sub.c t+.phi.) (1) EQU .phi.=tan.sup.-1 {L(t)-R(t)}/{1+L(t)+R(t)} (2)
where L(t) and R(t) represent the left and right channel signals, respectively, and .omega..sub.c represents the angular frequency of the carrier signal. A method for demodulating a modulated AM stereophonic signal of this type is known by which the main signal, L(t)+R(t), is envelope detected and the sub signal, L(t)-R(t) is synchronously detected. A diagram of a circuit operating by this detection method is shown in FIG. 1.
The received high-frequency signals, represented by the formulas (1) and (2), are converted to an IF (intermediate frequency) signal e.sub.i by a frequency converter circuit (not shown) and amplified by an IF amplifier 3. The IF signal e.sub.i is supplied to an envelope detector 4 where only the amplitude component of the signal is detected to provide the main signal, L(t)+R(t). The IF signal e.sub.i is also supplied to a divider circuit 5 where the phase-modulated component cos .phi. is removed, as described herein, and supplied to a synchronous detector 1. In the synchronous detector 1, the output of the divider 5 is synchronously detected with a signal sin .omega..sub.i t which is 90 degrees out of phase with the carrier signal to provide the sub signal, L(t)-R(t). Both main and sub signals are supplied to a matrix circuit 2 for demodulation into right and left channel signals.
The circuit of FIG. 1 includes a PLL (phase-locked loop) circuit 10 which provides a cos .phi. and sin .omega..sub.i t components for the divider 5 and synchronous detector 1. In the circuit 10, the IF signal e.sub.i is subjected to amplitude limitation by a limiter 6 to provide a generally rectangular signal cos (.omega..sub.i t+.phi.) which is free of the amplitude-modulated component. The output signal from the limiter 6 is supplied to a 90.degree. phase comparator 7 where it is frequency- and phase-compared with the output e.sub.o of a VCO (voltage-controlled oscillator) 11. The comparator output V.sub.1 is passed through a LPF (low-pass filter) 8 and amplified by a DC amplifier 9 the output of which is used for controlling the VCO 11. The VCO 11 has a free-running frequency .omega..sub.o equal to that of the IF signal e.sub.i so that the PLL circuit 10 is locked to the input angular frequency .omega..sub.i in such a manner that it is 90 degrees out of phase with the input signal. Since the output signal e.sub.o of the VCO 11 is sin .omega..sub.i t, it can be used as a switching signal for the synchronous detector 1. The signal e.sub.o is also supplied to a 90.degree. phase shifter 12 where it is phase-shifted by 90 degrees to provide a signal cos .omega..sub.i t which is supplied to one input of a synchronous phase detector 13, the other input of which is fed with the output cos (.omega..sub.i t+.phi.) of the limiter 6, to provide the cos .phi. signal which is used as a division signal.
The following equation represents the action of the synchronous phase detector 13: EQU cos (.omega..sub.i +.phi.).multidot.cos .omega..sub.i t=1/2{cos .phi.+cos (2.omega..sub.i t+.phi.}. (3)
Hence, by removing the cos (2.omega..sub.i t+.phi.) component with a filter, the cos .phi. component is provided.
The formula for the IF signal e.sub.i that is represented on the basis of the formulas (1) and (2) can be rearranged to the following: ##EQU1## (Here, with respect to e.sub.i, L and R, (t) indicating that these signals are functions of time, has been omitted.) In the divider circuit 5, the IF signal e.sub.i represented by the formula (4) is divided by the synchronous phase detection output cos .phi. to remove the cos .phi. component and provide an output which is represented by: EQU e.sub.i /cos .phi.=(1+L+R) cos .omega..sub.i t+(L-R) sin .omega..sub.i t.(5)
The division output represented by the formula (5) is supplied to the synchronous detector 1 where it is switched by the signal sin .omega..sub.i t into an (L-R) signal, that is, the sub signal.
The phase comparator 7 of the PLL circuit 10 delivers an output voltage V.sub.1 proportional to the cosine of the phase difference .DELTA..phi..sub.e between two input signals which is represented by: EQU .DELTA..phi..sub.e =cos.sup.-1 .DELTA..omega./K.sub.d ( 6)
where K.sub.d is the loop gain of the PLL circuit and .DELTA..omega. represents the difference between the angular frequency .omega..sub.i of the input signal e.sub.i and the free-running frequency .omega..sub.o of the VCO 11.
As is clear from the formula (6), when .DELTA..omega. is zero or when the input signal e.sub.i is equal to the free-running frequency of the VCO 11, .DELTA..phi..sub.e is 90 degrees and the output e.sub.o of VCO 11 is 90 degrees out of phase with the input signal e.sub.i thus achieving accurate detection of the sub signal. However, if the frequency of, for example, a local oscillation signal fluctuates slightly due to temperature drift or other factors, the frequency of the IF signal will also fluctuate, and as a consequence, .DELTA..omega. in the formula (6) is not zero. In this case, .DELTA..phi..sub.e varies with .DELTA..omega. as indicated by the formula (6) and the relation between the two parameters is typically represented by the solid line 201 in FIG. 2. If there is a difference between the free-running frequency of the VCO 11 and the frequency of the input signal e.sub.i, the output e.sub.o of VCO 11 is locked to the frequency of the input signal but it is not of phase with the input signal by a certain amount .DELTA..omega..sub.e. This makes accurate detection of the sub signal impossible.